Intra-Processor Parallel Architecture (C1)

Description: This module focuses on exploiting parallelism at the level of a single core (Intra Processor). Topics discussed include how the processors (architecture) can extract parallelism from a serial instruction stream using the concepts of instruction level parallelism (ILP), Data Level Parallelism (DLP), superscalar, out-of-order, and speculative execution. Additionally, the module is concerned with ways that the assembly language programmer (and hence the compiler) can identify parallelism in serial high level language as well as assembly language programs and enable the hardware to exploit this parallelism for improved performance. The module concentrates on ILP and DLP. For this end, an imaginary version of an extended MIPS processor is introduced, analyzed, and used for in-class demonstrations as well as homework assignments and exam questions. In addition, the module includes an introduction to the taxonomies of parallelism as well as the Amdahls law.

Recommended Length: Two lectures (~1:15 min)

Recommended Course: Computer Architecture, Computer Organization

Topics and Learning outcomes (per NSF/IEEE-TCPP PDC Curriculum):

  • [Architecture] Taxonomy: Flynn's taxonomy, data vs. control parallelism, shared/distributed memory
  • [Architecture, Algorithm] Amdahls law and its significance
  • [Architecture] Level of parallelism: (a) Bit level parallelism; (b) Instructional level; (c) Data level; (d) Task level
  • [Architecture] Superscalar (ILP): Describe opportunities for multiple instruction issue and execution (different instructions on different data)
  • [Architecture] SIMD/Vector (e.g., SSE, Cray): Describe uses of SIMD/Vector (same operation on multiple data items), e.g., accelerating graphics for games.
  • [Programming] Amdahl's law: Know that speedup is limited by the sequential portion of a parallel program, if problem size is kept fixed
  • [Programming] Speedup: Understand how to compute speedup, and what it means

Lecture Material: [ PDF ] [ PPT ]

Sample Source Code:

Pedagogical Notes: available for instructors only

Sample Exam Question: available for instructors only


Jun '15: Qasem speaks at HPC Workshop at Prairiw View A & M

Oct '14: Paper accepted at SIGCSE15

Oct '14: Short paper accepted at EduHPC14 (co-located with SC14)

Aug '14: First regional workshop held at Texas State

May '14: Call for participation in first regional workshop

Mar '14: Qasem serves as penelist in SIGCSE special session on PDC

Nov '13: Poster presented at Supercomputing conference

Sep '13: Paper accepted at EduPDHPC13

Aug '13: Qasem participates in CSinParallel Four Corners Workshop

Jul '13: Qasem receives Early Adopter grant

Mar '13: Qasem presents at NSF Showcase at SIGCSE13

Jan '13: Five new modules implemented

Aug '12: Burtscher receives Early Adopter grant


Apan Qasem (PI)
Department of Computer Science
Texas State University
601 University Dr
San Marcos, TX 78666

Office: Comal 307A
Phone: (512) 245-0347
Fax: (512) 245-8750
E-mail: apan "AT" txstate · edu